Forward error control coding

ABSTRACT

A system and method for providing error control coding for backhaul applications are disclosed. Data is first encoded using Reed-Solomon (RS) coding. The output RS blocks are then turbo coded. The size of the output RS blocks is selected to match the input of the turbo encoder. The bits from the RS blocks may be interleaved to create the input turbo blocks. Cyclic Redundancy Check (CRC) parity bits may be added to the data prior to RS coding.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a continuation of U.S. Pat. Application Serial No.17/141,095 filed Jan. 4, 2021, which is a continuation of U.S. Pat.Application Serial No. 16/292,693 filed Mar. 5, 2019, which also claimsbenefit of U.S. Pat. Application No. 14/580,622 filed on Dec. 23, 2014,all of which are incorporated herein by reference.

BACKGROUND

Wireless users require high-speed connections that support real timevideo, streaming music, and other multimedia applications. As a result,demands on wireless networks approach the broadband speeds and userexperience provided by traditional DSL and cable modem wireline service.Wireless networks continue to evolve to next-generation packetarchitectures capable of supporting enhanced broadband connections withthe introduction of 4G systems.

The higher speeds and capacity provided by 4G wireless networks putstrain on backhaul networks and the carriers providing backhaul servicesas the transport requirements increase. Providers are shifting fromtraditional TDM transport in 2G and 3G networks to packet transport tosupport higher data rates, reduce network latency, and support flexiblechannel bandwidths in 4G networks. The backhaul networks requireefficient Bit-Error-Rate (BER) performance to support 4G mobilenetworks.

SUMMARY OF THE INVENTION

Embodiments provide error control coding mechanisms for backhaulapplications. Data is first encoded using Reed-Solomon (RS) coding. Theoutput RS blocks are then turbo coded. The size of the output RS blocksis selected to match the input of the turbo encoder. The bits from theRS blocks may be interleaved to create the input turbo blocks. CyclicRedundancy Check (CRC) parity bits may be added to the data prior to RScoding.

A transmitter provides forward error correction. The transmittercomprises a CRC parity bit generator that appends CRC bits to incomingdata, a RS coder that creates RS blocks from the incoming data and CRCbits, an interleaver that interleaves symbols in the RS blocks to createturbo coder input blocks, and a turbo encoder that uses the turbo coderinput blocks to create a signal to be sent to a receiver. Thetransmitter circuit may comprise a Digital Signal Processor (DSP) thatprovides hardware for the turbo encoder and CRC parity bit generator.Software instructions running on the DSP may provide the RS coder andthe interleaver. The size of the RS blocks may be selected to match theinput block size of the turbo coder so that an integer number of RSblocks are interleaved to create the turbo coder input blocks. Theinterleaver may sequential fill the turbo input blocks with symbols fromsuccessive RS blocks. The CRC parity bit generator and the turbo encodermay operate using parameters defined in the LTE standard.

A receiver decodes forward error corrected signals. The receivercomprises a turbo decoder that decodes received signals to create turbooutput blocks, a de-interleaver that de-interleaves the turbo outputblocks to create RS input blocks, a Reed-Solomon decoder that receivesthe RS input blocks and generates decoded output data, and a CRC paritybit check circuit that evaluates CRC bits in the decoded data. Thereceiver may further comprise a DSP that provides hardware for the turbodecoder and CRC parity bit check circuit. Software instructions runningon the DSP may provide the RS decoder and the de-interleaver. The sizeof the RS blocks may be selected to match the output block size of theturbo decoder so that an integer number of RS blocks are de-interleavedfrom the turbo decoder output blocks.

BRIEF DESCRIPTION OF THE DRAWINGS

Having thus described the invention in general terms, reference will nowbe made to the accompanying drawings, wherein:

FIG. 1 is highly simplified block diagram of a system that mayincorporate embodiments of the invention;

FIG. 2 is a block diagram of a system using a combination of RC codingand turbo coding according to one embodiment;

FIG. 3 illustrates interleaver operation in an embodiment with exampleblock size 6144 and three turbo blocks;

FIG. 4 is a flowchart illustrating a method for encoding data to provideforward error correction according to one embodiment; and

FIG. 5 is a method for decoding forward error corrected signalsaccording to one embodiment.

DETAILED DESCRIPTION

The invention now will be described more fully hereinafter withreference to the accompanying drawings. This invention may, however, beembodied in many different forms and should not be construed as limitedto the embodiments set forth herein. Rather, these embodiments areprovided so that this disclosure will be thorough and complete, and willfully convey the scope of the invention to those skilled in the art. Oneskilled in the art may be able to use the various embodiments of theinvention.

FIG. 1 is highly simplified block diagram of a system 100 which is partof a cellular communications network, such as a 3GPP Long Term Evolution(LTE) network. Base stations 101, 102 serve user equipment (UE) 103, 104and other devices (not shown). Base stations 101, 102 may be, forexample, LTE eNodeBs. Backhaul links 105-107 allow bases stations 101,102 to communicate with each other or with core network 108.

Channel coding between base stations and UEs in an LTE network includesCRC and turbo coding schemes. LTE adopts turbo coding as the channelcoding for the Physical Downlink Shared Channel (PDSCH), for example.Turbo coding provides sufficient BER for communications between basestations and UEs, but a more efficient BER is required for backhaullinks 105-107.

Because turbo coding processors are already present in LTE base stationsfor use in UE communications, this available hardware can beincorporated into the design of error control coding for backhaulsystems. LTE turbo codes may be used as the core part for error controlcoding. To cope with the error floor for turbo codes at highSignal-to-Noise Ratio (SNR), an outer code may be used to remove theresidual errors of turbo codes. In embodiments disclosed herein, the RSblock code is selected as the outer code for a Forward Error Correction(FEC) system. RS code offers excellent error correcting capability andhas the maximum code rate for the number of corrected symbols.

FIG. 2 is a block diagram of a system using a combination of RC codingand turbo coding according to one embodiment. Input data 201 is receivedat transmitter 202, which applies FEC coding and transmits the data toreceiver 203. Receiver 203 decodes the data to generate received decodeddata 204. Transmitter 202 may be in base station 101, for example, andmay use FEC for data sent over backhaul link 105 to base station 102which includes receiver 203.

Transmitter 202 FEC adds CRC in block 205 and then RS encoding in block206. To maximize concatenation gain, a symbol interleaver 207 is usedbetween turbo encoder 208 and the RS encoder 206 so that symbol errorsfrom the turbo code are dispersed between more than one RS code. Thismaximizes the error correcting capability of the concatenated code. Inone embodiment, turbo encoder 208 may be a turbo hardware accelerator inan LTE base station. The RS encoder 206 and symbol interleaver 207 maybe performed by software on the same DSP as the turbo hardwareaccelerator. In one embodiment, a single DSP core is dedicated to FECprocessing to minimize data transfer among components in thetransmitter. The output of turbo decoder 208 is transmitted to receiver203.

Receiver 203 decodes the data received from transmitter 202. Receivedsignals are processed in turbo decoder 209 and then symbolde-interleaver 210. The signal is then RS decoded in block 211 and CRCchecked in block 212 to generate received decoded data 204. Similar totransmitter 202, turbo decoder 209 may be a turbo hardware acceleratorDSP in an LTE base station, while the symbol de-interleaver 210 and RSdecoder 211 may be performed by software on the same DSP as the turbohardware accelerator. In one embodiment, a single DSP core is dedicatedto error correction processing to minimize data transfer amongcomponents in the receiver.

The parameters used for the turbo+RS concatenated code may be selectedto facilitate reuse of the hardware turbo modules in an LTE basestation. LTE turbo code with code rate matching may be used to provide anear continuous range of code rates in the Modulation and Coding Scheme(MCS) table. In one embodiment, three block size of turbo codes {6144,3072, 1024} may be used to provide a compromise between the performanceand latency of FEC encoding/decoding. Additionally, the maximum numberof turbo iterations is varied to improve this tradeoff. The exact outputblock size of the turbo encoder is varied to achieve maximum efficiencyof the frame structure and minimize the number of unused filler bits.

The output block size of RS codes from RS encoder 206 should match theinput block size of turbo codes in turbo encoder 208. The RS code isspecified by three parameters (n,k, t), where n is the output block size(in symbols), k is the input block size in symbols, and t is the numberof symbol errors that can be corrected. The three parameters are relatedwhere k = n -2t. To simplify software implementations of the RSencoder/decoder, RS over the field GF(2⁸) may be used so that the codesymbols correspond to whole bytes. Two shortened RS codes may be used:(192,184,4) and (128,122,3). The first code (192,184,4) is used withturbo block sizes 6144 and 3072 bits. The second code (128,122,6) isused with turbo block size 1024 bits.

Table 1 lists RS codes for different turbo block sizes. For a turboblock size of 6144, there are four RS blocks of the constituent code(192,184,4) per a single turbo block. For a turbo block size of 3072,there are two RS blocks of the constituent code (192,184,4). For a turboblock of size 1024, there is a single RS block of the constituent code(128,122,3).

TABLE 1 Turbo Block Size (bits) RS Code Number of RS blocks per Turboblock 6144 (192,184,4) 4 3072 (192,184,4) 2 1024 (128,122,3) 1

The input data block to the RS encoder is appended by CRC parity bitsfor error detection at the receiver. In one embodiment, a CRCaccelerator on a bit rate coprocessor (BCP) for CRC encoder/decoder isused. The length of the CRC parity bits depends on the size of the turboblock size. The CRC polynomials for LTE may be used for generating theparity bits. Table 2 lists the length of the CRC parity check bits forthe turbo block sizes used in the example of Table 1.

TABLE 2 Turbo Block Size (bits) Length of CRC Parity Bits 6144 24 307216 1024 8

The possible information block sizes for different turbo block sizes aresummarized in Table 3. The information data block size is the turboblock size minus parity bits of the RS minus the CRC bits.

TABLE 3 Turbo Block Size (bits) Length of Information Block Size (bits)6144 5864 3072 2928 1024 968

To increase the FEC efficiency, multiple turbo blocks may be interleavedtogether before RS encoding. This distributes the turbo decoder erroramong more turbo blocks for more error protection. Up to three turboblocks may be interleaved together, and the corresponding number of RSblock is multiplied accordingly.

As illustrated in FIG. 2 , the FEC encoder is comprised of fourcomponents: CRC generator, RS encoder, interleaver, and Turbo encoder.

The length of the CRC parity bits depends on the turbo block size asillustrated in Table 2. The generator polynomials from the LTE standardmay be used for the different size CRC generation:

g_(crc24) = D²⁴ + D²³ + D¹⁸ + D¹⁷ + D¹⁴ + D¹¹ + D¹⁰ + D⁷ + D⁶ + D⁵ + D⁴ + D³ + D + 1

g_(crc16) = D¹⁶ + D¹² + D⁵ + 1

g_(crc8) = D⁸ + D⁷ + D⁴ + D³ + D + 1

The encoding and decoding is done similar to LTE to enable the reuse ofthe hardware accelerator.

After adding the CRC parity bits, the input block size is segmented toRS blocks. The number of RS blocks depends on the turbo block size andthe number of turbo blocks. For example, with three turbo blocks of size6144, then there are a total of 12 RS (192,184,4) blocks; or with oneturbo block of size 1024, then there is one RS (128,122,3) block.

The interleaver maps the output RS blocks to the input of turbo blocks.The objective of the interleaver is to spread any possible error fromthe turbo decoder among as many RS blocks as possible to maximize thecorrecting probability. The RS output is in symbols (i.e., 8 bits),while the unit in the turbo block is a bit.

FIG. 3 illustrates the interleaver operation in an embodiment with blocksize 6144 and three turbo blocks 301A-C. In this example, there are atotal of 12 RS blocks (192,184,4) 302A-L. The turbo blocks 301A-C arefilled sequentially by symbols from successive RS blocks 302A-L. Forexample, the first 8 bits in the first turbo block 301A are from thefirst symbol (i.e., 8 bits) of the first RS block 302A, the second 8bits of the first turbo block 301A are the first output symbol from thesecond RS block 302B, and the 12^(th) set of 8 bits in the first turboblock 301A are the first output symbol in the 12^(th) RS block 302L, andso on as shown in FIG. 3 . The whole eight bits of each RS symbol aresequentially placed in the corresponding locations in the turbo block.

This interleaving may be described algebraically as follows. Assume Mturbo blocks of length L bits and N RS blocks per turbo block each RSblock has output size of K=L/8N symbols. The output symbols of all RSblocks may be arranged in a matrix of size MN × K. Each row contains theoutput symbols of the corresponding RS block. The matrix may beconverted to a column vector by raster scanning column wise (i.e., firstcolumn then second column and so on). The vector of symbols is thenconverted to a vector of bits by expanding each symbol to 8 bits. Thisgenerates long vector of length LMbits. The vector is then converted toa matrix of size L × M with each column corresponding to an input turboblock of size L bits.

The turbo encoding may be performed using a bit rate coprocessorhardware accelerator. An LTE rematching module may be used to generatethe exact output block size as described in the MCS table. The RSencoder uses standard shortened RS blocks as specified in Table 1.

FIG. 4 is a flowchart illustrating a method for encoding data to provideforward error correction according to one embodiment. In step 401, CRCparity bits are appended to incoming data. In step 402, RS encodedblocks are created from the incoming data and CRC bits. In step 403,symbols in the RS blocks are interleaved to create turbo input blocks.The interleaving may sequential fill the turbo input blocks with symbolsfrom successive RS blocks. In step 404, the turbo input blocks are turboencoded to create a signal to be sent to a receiver.

The CRC parity bits and turbo encoding of the input blocks may beperformed using DSP hardware. Software instructions on the DSP may beused to create the RS encoded blocks and interleave the RS blocks. Thesize of the RS blocks may be selected to match the input block size ofthe turbo coder so that an integer number of RS blocks are interleavedto create the turbo coder input blocs so that an integer number of RSblocks are interleaved to create the turbo coder input blocks. The CRCparity bits and the turbo encoder operation may be compatible with theLTE standard.

FIG. 5 is a method for decoding forward error corrected signalsaccording to one embodiment. In step 501, received signals are turbodecoded to create turbo output blocks. In step 502, the turbo outputblocks are de-interleaved to create RS input blocks. In step 503, the RSinput blocks are RS decoded to generate decoded output data. In step504, CRC parity bits in the decoded data are evaluated.

The turbo decoding and evaluating CRC parity bits may be performed byDSP hardware. Software instructions executing on the DSP may decode theRS input blocks and de-interleave the turbo output blocks. The size ofthe RS blocks is selected to match the output block size of the turbodecoder so that an integer number of RS blocks are de-interleaved fromthe turbo decoder output blocks.

Although the detailed example described above is used in connection withan LTE system, it will be understood that embodiments may be used withsystems complying with any wireless protocol or standard.

Many modifications and other embodiments of the invention will come tomind to one skilled in the art to which this invention pertains havingthe benefit of the teachings presented in the foregoing descriptions,and the associated drawings. Therefore, it is to be understood that theinvention is not to be limited to the specific embodiments disclosed.Although specific terms are employed herein, they are used in a genericand descriptive sense only and not for purposes of limitation.

What is claimed is:
 1. A transmitter circuit providing forward errorcorrection, comprising: a Cyclic Redundancy Check (CRC) parity bitgenerator that appends CRC bits to incoming data; a Reed-Solomon (RS)coder that creates RS blocks from the incoming data and CRC bits; aninterleaver that interleaves symbols in the RS blocks to create turbocoder input blocks; and a turbo encoder that uses the turbo coder inputblocks to create a signal to be sent to a receiver.
 2. The transmittercircuit of claim 1, further comprising: a Digital Signal Processor (DSP)that provides hardware for the turbo encoder and CRC parity bitgenerator.
 3. The transmitter circuit of claim 2, further comprising:software instructions running on the DSP to provide the RS coder and theinterleaver.
 4. The transmitter circuit of claim 1, wherein the size ofthe RS blocks is selected to match the input block size of the turbocoder so that an integer number of RS blocks are interleaved to createthe turbo coder input blocks.
 5. The transmitter circuit of claim 1,wherein the interleaver sequential fills the turbo input blocks withsymbols from successive RS blocks.
 6. The transmitter circuit of claim1, wherein the CRC parity bit generator and the turbo encoder operateusing parameters defined in a Long Term Evolution (LTE) standard.
 7. Amethod for encoding data to provide forward error correction,comprising: appending Cyclic Redundancy Check (CRC) parity bits toincoming data; creating Reed-Solomon (RS) encoded blocks from theincoming data and CRC bits; interleaving symbols in the RS blocks tocreate turbo input blocks; and turbo encoding the turbo input blocks tocreate a signal to be sent to a receiver.
 8. The method of claim 7,further comprising: creating CRC parity bits and turbo encoding theinput blocks using Digital Signal Processor (DSP) hardware.
 9. Themethod of claim 8, further comprising: executing software instructionson the DSP to create the RS encoded blocks and interleave the RS blocks.10. The method of claim 7, wherein the size of the RS blocks is selectedto match the input block size of the turbo coder so that an integernumber of RS blocks are interleaved to create the turbo coder inputblocs so that an integer number of RS blocks are interleaved to createthe turbo coder input blocks.
 11. The method of claim 7, wherein theinterleaving sequential fills the turbo input blocks with symbols fromsuccessive RS blocks.
 12. The method of claim 7, wherein the CRC paritybits are generated and the turbo encoder operates using parametersdefined in a Long Term Evolution (LTE) standard.
 13. A receiver circuitdecoding forward error corrected signals, comprising: a turbo decoderthat decodes received signals to create turbo output blocks; ade-interleaver that de-interleaves the turbo output blocks to createReed-Solomon (RS) input blocks; a Reed-Solomon decoder that receives theRS input blocks and generates decoded output data; and a CyclicRedundancy Check (CRC) parity bit check circuit that evaluates CRC bitsin the decoded data.
 14. The receiver circuit of claim 13, furthercomprising: a Digital Signal Processor (DSP) that provides hardware forthe turbo decoder and CRC parity bit check circuit.
 15. The receivercircuit of claim 14, further comprising: software instructions runningon the DSP to provide the RS decoder and the de-interleaver.
 16. Thereceiver circuit of claim 1, wherein the size of the RS blocks isselected to match the output block size of the turbo decoder so that aninteger number of RS blocks are de-interleaved from the turbo decoderoutput blocks.
 17. A method for decoding forward error correctedsignals, comprising: turbo decoding received signals to create turbooutput blocks; de-interleaving the turbo output blocks to createReed-Solomon (RS) input blocks; Reed-Solomon decoding the RS inputblocks to generate decoded output data; and evaluating Cyclic RedundancyCheck (CRC) parity bits in the decoded data.
 18. The method of claim 17,further comprising: turbo decoding the received signals and evaluatingCRC parity bits and using Digital Signal Processor (DSP) hardware. 19.The method of claim 18, further comprising: executing softwareinstructions on the DSP to decode the RS input blocks and tode-interleave the turbo output blocks.
 20. The method of claim 17,wherein the size of the RS blocks is selected to match the output blocksize of the turbo decoder so that an integer number of RS blocks arede-interleaved from the turbo decoder output blocks.